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HPA MMIC设计中最难的部分
2008-07-01
当然就是匹配网络了。首先看看在HPA MMIC中，匹配网络的作用：
- Present the optimum source and load impedances to the transistors;
- Divide or combine the RF power;
- For the input and interstage-matching network, realise a frequency dependent loss;
- Supply the DC bias to the transistors;
- Enhance the stability of the amplifiers.
这最基本的五条，看似简单，但是任意一条拿出来都可以说上一大堆Design Options，比如DC Bias：在MMIC中首先要根据电流大小及金属的最大可承受电流密度，计算其宽度下限，然后再选定宽度的基础上取其长度，使其完成射频扼流及器件输出阻抗的虚部补偿；当考虑到版图布局的时候，还要仔细选择Bias Stub的位置和形状等等。总而言之，匹配网络的设计是PA设计中最纷繁复杂而又最最重要的部分。那么简要说明一下HPA MMIC中匹配网络设计的程序及一些注意事项：
- 一定要首先从输出匹配网络开始，而且要花最大精力保证输出匹配良好--这点非常重要。根据load-pull测试的数据以及HPA末级并联的器件数目，首先设计DC Bias部分将匹配网络的原阻抗转换为实阻（中心频率处），然后利用对称性及N端口网络与2端口网络的互换特性设计多级匹配，具体的形式可以根据实际情况确定：L型低通、L型高通、Pi型以及分布式匹配等等；
- 如果说输出匹配是重点，那么级间匹配就是难点了，它所需要完成的任务最多，涉及的方面也最多：虚部吸收、DC Block、Power Divider等等，太复杂了就不详细说了；
- 输入匹配相对比较好解决，有了前面输出匹配网络和级间匹配网络的完成，相信输入匹配不在话下了：DC Block、Power Divider、稳定网络。
- 稳定性的分析比较复杂，HPA中的振荡大概可以分为四类：环路振荡、低频振荡、奇模振荡和参量振荡，每一种振荡的机理都各不相同，当然解决办法也就各异。通常可以采用的解决方案包括：RC并联网络（低频振荡、环路振荡、参量振荡）、并联电阻（奇模振荡）、片上及片外Large Decoupling（低频振荡）等等。
另外简单说一下关于热稳定性的设计考量。小于1GHz的PA，热设计主要在片外进行；大于30GHz的PA，则一般不需要考虑热设计；1～30GHz的PA MMIC，则要仔细研究一下热稳定性：电流增益崩塌、thermal runaway等。器件间距及镇流电阻是解决方案的方向，以及工艺上的热分流结构及热沉。
先简略说这么多，日后在详细总结报告之。
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从硬盘的角落里翻出一张照片，去年组织去妙峰山：
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青春就像是卫生纸，看着挺多的，用着用着就没有了。
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北京的这个夏天，天天下雨，真是凉快。
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最佳负载阻抗 + Load-pull
2008-06-30
The following methods to determine the optimum load impedance were considered:
(1). The use of the so-called Cripps method.
This method uses a simplified model of the transistor, which can be obtained from small-signal S-parameter measurements at the bias point of interest and knowledge of the DC IV curves. With the help of this information it is possible to construct load-pull contours and the optimum load impedance can be determined. The Cripps method was not used because of the following limitations:
A. The DC IV curves are not always similar to the AC IV curves;
B. Other essential information for the high-power amplifier design is missing e.g. the input impedance of the transistor under large-signal conditions when it is loaded with the optimum load impedance;
C. Modeling of the external part of a transistor with only the drain to source capacitance is too simplistic. Certainly for large transistors, as it is the case for the high-power amplifiers, the influence of the drain-source resistance and the parasitic inductances on the external optimum impedance can no longer be neglected. However, if no large-signal transistor model or load-pull measurement set-up is available it can give a reasonable estimation of the optimum load impedance.
(2). The use of load-pull simulations performed with the help of the large-signal transistor model and the contour test bench available in the Agilent Series IV simulation software.
Comparison with load-pull measurements shows, that the transistor model will give a good estimation of the location of the optimum load impedance in the case of maximum output power. This becomes more difficult if an optimum load impedance for maximum power added efficiency is searched. This is due to the overestimation of the drain current by the transistor model.
(3). The use of load-pull measurements is still the preferred method to determine the optimum load impedance.
When this type of measurements is performed, information becomes available regarding the load impedance of the interstage-matching network.
The load impedance, which must be presented at the output of the transistors, is dependent on the input power. Under small-signal conditions, the optimum load impedance for maximum output power, PAE and power gain is the same. The load that is found for this case is the conjugated of the output impedence of the transistor when the input is simultaneously conjugated matched with the source impedance. When the input power is increased, the real part of the load impeance starts to change from Rds to a load that will guarantee maximum voltage and current swing. Under these non-linear conditions the optimum load for maximum output power and the one for maximum PAE are unequal. For a number of amplifiers, a compromise between these two impedance is used. The results show that the real part of the load for maximum PAE is higher than the one for maximum output power. The load for maximum output power is almost constant as a function of compression level. This is as expected not the case for the maximum efficiency load.
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上次load-pull测试出现的奇怪情况：6GHz下Zopt为容性，现在似乎找到了比较可信的解释。小信号状态下的Zopt有别于大信号下的Zopt，但是大信号下P1dB、最大线性功率和饱和功率所对应的Zopt是统一的，所以在load-pull测试中，可以以这三个指标的任意一个作为标准。还想再做一次load-pull，可是GPIB转USB接口卡悬而未决，还得等待几天。
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又一次高考成绩揭晓，几家欢喜几家愁，命运不济的人真是可怜。想成就任何一件事情，都需要各种各样的主客观条件齐备，一块无法弥补的短板将永远给你一只漏桶。无话可说。
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周末在地质所打篮球。好久没有玩了，跑起来气喘吁吁，不过手感和技术还没有丢，呵呵。另外，持续一年多的健身效果显现：当我带球突破的时候防守人员纷纷退后，然后被冠以“超音速推土机”。可惜球场太硬，又穿了一双鞋底很厚的卡特，所以脚踝受不了。完事之后和地质所的哥们说起两边关于二号楼的纠纷，嘿嘿，管我X事，我是来打篮球的。
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Strong demand pull fires up GaN foundries
2008-06-26
From: compoundsemiconductor.net
Cree and TriQuint have both rolled out competing GaN foundry services amid strong interest in the high-power RF technology at the 2008 International Microwave Symposium.
In each case military applications are providing a strong driving force in developing GaN devices, attracted by characteristics like high power density and high-temperature operation.
Both companies are still involved in DARPA's Wide Bandgap Semiconductor Technology initiative, with TriQuint in particular indicating to compoundsemiconductor.net in Atlanta that its GaN efforts are being supported by the recent award of the third phase of funding within this program.
TriQuint and Cree also both contributed to the event's swarm of GaN power amplifier product releases, which ironically are now encouraging other companies to design their own devices.
“Buying off the shelf tends to attract people into design,” said John Palmour, executive vice president for advanced devices at Cree. “Thanks to that in part there will be plenty of military and some R&D use of the foundry.”
TriQuint's foundry services will initially encompass the frequency range from DC to 18 GHz, which Cree is also intending to support.
The two foundries will share another common approach in producing devices from GaN epiwafers grown on SiC substrates. TriQuint is working with its epiwafer supplier IQE to move from 3-inch to 4-inch wafers. If Cree is not already using 4-inch GaN wafers, as the industry's dominant supplier of SiC substrates it is surely not far away either.
However, before any squabbles can break out between these two companies over which was the first commercial GaN foundry, a third player may wish to have a say.
Germany's United Monolithic Semiconductors (UMS) has been working on developing GaN devices in a European collaboration since 2006 and is also looking at a move to 4-inch wafers. Here the military interest is provided by aerospace firm - and part owner of UMS - EADS.
NXP Semiconductors adds a high-volume angle, expecting the collaboration to deliver commercial 100 W GaN devices for wideband-CDMA base stations in 2009. Mark Murphy, NXP's spokesperson for the project, said that the collaboration is currently achieving the company's reliability targets for this product line in comparisons with its existing silicon LDMOS products.Specific processes used by the collaboration are out of bounds to other customers, but UMS still offers GaN foundry services elsewhere to help enhance the technology's overall commercial viability.
This European collaboration, led by the Fraunhofer Institute for Applied Solid-State Physics, takes the view that there is room for three major GaN players globally. According to Murphy, Japan's Eudyna and Cree in the US currently take the top slots. Although Europe's effort is a collaboration reliant on a III-V foundry rather than a single company, he believes that there will ultimately be one major GaN player in Asia, one in North America and one in Europe.
Richard: 还是那句话，我们只是看热闹的。唉......
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单芯片实现LTE和WiMax前景分析
2008-06-25
From: eetchina.com
LTE和WiMax之间唯一最重要的相似性在于均采用正交频分复用(OFDM)信令。两种技术也均采用Viterbi和turbo加速器来实现前向纠错。
从芯片设计工程师的观点来看，如果你要在同一芯片或芯片组内支持两种制式的话，就非常有可能广泛地重用各种门。从软件无线电(SDR)的观点来看，机会更为诱人。灵活性、门重用以及可编程性似乎就是应对WiMax-LTE多模式挑战的答案，而那可能意味着要采用软件无线电技术。
LTE和WiMax可能就是OFDM这颗“蚕豆”上的“两片豆子”，但是，它们并不是孪生的。它们之间存在三个重要差异：
1. 两者均在下行链路中采用正交频分多址接入(OFDMA)。然而，WiMax通过在一个宽的信道上处理所有的信息而对信号利用率进行最优化。相比之下，LTE把可用频谱组织为更小的频段。
WiMax为高信道利用率付出一定的代价，但是，因为处理那么多的信息可能需要1000点快速傅立叶变换。LTE用16点FFT就能完成。这相当于功耗更大，因为难以在有效的LTE设计中加入有用的WiMax硬件。然而，使用软件无线电原理的一种架构能够重新配置它的FFT函数以实现更低的功耗。
2. LTE的上行信令采用单一载波频分多址接入(SC-FDMA)，而WiMax坚持采用OFDMA。基于OFDM的系统的主要问题之一就是它们具有高的峰值-平均功率比。在市场营销中引证的平均功率指标并没有展示整个情况。遗憾的是，系统的功率放大器必须被设计为处理峰值功率，而功率放大器也成为手机中一个的耗电大户。
LTE之所以特别选择SC-FDMA就是为了提高功率放大器的效率。“如果你通过改变调制制式就能够把效率从5%改善为50%，那么，你就可以节省大量的电池电量，”多模式专业提供商Coresonic AB公司的首席系统架构师Anders Nilsson表示。WiMax的OFDMA具有大约10dB的峰值平均功率比，而LTE的SC-FDMA的峰值-平均功率比大约为5dB。
这一差异也影响基带芯片，Nilsson补充说，因为需要在上行链路中支持两种调制方式。可编程解决方案可以灵活到足以重用门并在LTE模式保持低功耗。
3. 尽管IEEE 802.13e标准以及演进中的LTE标准支持频分双工(FDD)以及时分双工(TDD)，WiMax实现主要采用的是TDD。LTE似乎在FDD方向上领先，因为它是真正的全双工工作：各个邻近的信道被用于上行和下行链路。因此，LTE具有更好的下行数据率指标，尽管所付出的代价是对前向纠错有非常严格的延迟要求。底线就是WiMax射频要更为简单一些。
这些差异使得要设计支持两种标准的芯片或芯片组就更加困难，但是，通过调和而不是竞争，结果可能更加易于解决网络基础设施上存在的问题。当然，从手机设计工程师的观点来看，显然没有赢家。
电池的寿命以及芯片或芯片组的功效是它们取得市场成功的关键，一位专门从事无线电测试和设计的独立咨询师Fannie Mlinarsky说道。功耗是WiMax和LTE面临的大问题，因为Mbps的性能意味着运行DSP困难并且使得芯片更加耗电。
通过软件无线电实现多模解决方案
尽管软件无线电的确享有昂贵和过分宣传的坏名声，但是，电信芯片设计工程师们业已采用软件无线电技术也是事实。他们需要——也完全是为了——适应不断演进的各种标准所带来的变化。
软件无线电的经典定义就是让通用处理器构成的阵列实质上的在软件中运行所有的功能。这种方法可能昂贵且可能无法达到高数据率技术，如WiMax和LTE，要求的价格/性能目标，无线设计独立顾问Fannie Mlinarsky表示。
另一方面，采用创新硬件架构的新方法似乎就要抓住眼下的黄金时代。长期从事OFDMA芯片设计的Wavesat公司早已进入该领域。这家公司与移动产品ODM Compal Communications公司签署了协议，以开发移动WiMax产品；而与日本的电信公司Willcom签署协议，利用Wavesat公司的Odyssey 8500芯片组开发XG-PHS宽带无线电产品。
Wavesat公司高级副总裁Vijay Dube表示，实际上该芯片组是能够实现任何基于OFDM技术的4G平台。Odyssey 8500就是以8颗DSP内核为基础。
Coresonic AB还拥有基于新架构——单一指令流多任务(SIMT)——的多模式平台。SIMT能够实现非常长指令字架构的性能，但是，具有较低的控制开销以及更低的程序和存储器使用率，该公司首席执行官Rich Clucas表示。
Mlinarsky表示，面向LTE以及WiMax的多模式基带解决方案充满挑战，但是，因若干原因所致，设计前端芯片才是真正令人畏惧的，关键在于这两个标准覆盖的是大约4GHz的宽频谱。LTE可能要支持900-MHz至1,900-MHz带宽；而WiMax必须根据地区情况抢夺可用的频谱，可能的工作范围是2.3 GHz至3.5 GHz。
BitWave半导体公司的可编程RF收发器承诺提供一种克服多模式挑战的解决方案。该公司首席市场官Russell Cyr表示，BitWave的原型软收发器RFIC已经提供给选定的ODM。采用该技术的手机以及Femtocell(家庭网)应该在明年发布。BitWave的技术通过数字方法调整无源电路元件，从而可对诸如LNA、滤波器以及混频器这样的模拟功能进行编程。
利用这些正在发挥作用的新技术，要做一点融合均要经历漫长的道路。LTE在很大程度上仍然处于发展阶段，WiMax也没有停滞不前，Forward Concepts公司总裁Will Strauss表示，“802.16m工作组正在着手完成各种改进，以使之具有看起来非常像蜂窝电话，如跨区切换的功能。”Richard: 令人眼花缭乱的各种标准，大家公说公有理，婆说婆有理，谁也搞不定谁。前段时间刚说过UWB没有前途，WiMax才是正统；现在又说WiMax也不行了，未来是LTE的天下。有的人是做了充分的深入调查，作出一个判断；有的人则是抱大腿，跟着巨头走；也有的人，不知道如何选择，不如来个一锅端。基带厂商们，面对众多标准应接不暇，可能还要整天开会讨论把赌注投到哪里；而前端厂商们则高兴了：最好隔一天出来一个标准，不管你什么标准，总要用到我的PA和LNA吧？
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Power Amplifier MMIC Flow
2008-06-18
1. Determine Optimum Bias Point for Required Output Power;
2. Design of Biasing Network;
3. Transistor Stability Analysis, Zsource Calculation for MAG;
4. Load-pull Analysis to Determine Optimum Zload for Required Pout;
5. Design of Matching Network;
6. Optimization, Yield Analysis and Design Centering;
7. Layout Gneration (EM Analysis);
8. Verification for Wireless Communication Standard.
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VBIC Modeling for InGaP/GaAs HBT
2008-06-17
长叹一口气......该死的VBIC模型，终于可以不再折磨我那少得可怜的脑细胞了。
湖哥走的时候将MMIC PA的工作留给我，到现在他毕业整整一年了，但是工作几乎停滞不前。电路的拓扑结构和工艺早就OK了，但是在设计的时候没有HBT器件模型，没有Load-pull测试数据--当我试图去做这些的时候，我们微波探针台上的探针挂了，Load-pul只要一加电就振荡。知道上月，卡尔休斯的探针和新的Load-pull系统都到位，于是数据搞定了。测试比较简单--只要你有测试手段，问题是测试之后的数据处理，譬如提取模型参数、设计匹配网络等等。
那么，当下最要紧的是建模了--没有模型，设计出来的是什么只有鬼知道。对于HBT来说，常见的模型是SGP（Spice Gummel-Poon）和VBIC（Vertical Bipolar Inter-Company），VBIC模型由于包括了重要的自热效应、弱雪崩击穿效应、准饱和效应等，所以应用更为广泛。一般代工厂都会提供SGP和VBIC两种模型供电路设计者使用，强烈推荐VBIC。当然，VBIC也不是最佳选择--比如在表征多指功率HBT器件的热效应上VBIC就无能为力，似乎最有前途的办法就是自己针对自己的特殊应用建立一套模型--譬如葛霁师兄所作的工作，针对GaAs和InP HBT自己建模。有前途，但是看看师兄桌上草稿纸上大段大段的物理公式，还有他和金老师整天讨论全耗尽啊、内建电势啊、电流阻挡效应啊、碰撞电离啊，我辈可知难而退矣。还是做一个差不多的VBIC模型吧，而且前面已经有一些师兄做过类似的工作。86个参数，针对InGaP/GaAs HBT进行优化之后，实际上需要提取的只有40个左右了，尽管如此，工作量还是非常大的。简单来说，如果给你一个三元方程，其中每个未知数互相之间又相互关联，你认为用数值拟合是否简单？更何况这里是40个未知数。好了，废话少说吧，有兴趣的兄弟可以看看我的总结：
《VBIC模型及参数提取--for InGaP/GaAs HBT》
测试了同一个Wafer上不同区域的几个器件，测试结果表明一致性还是挺好的，所以建立的模型对于不同器件的拟合也是不错的--直流拟合稍差，S参数拟合挺好，考虑到工艺偏差，可以满足设计要求。
嗯，接下来的工作就比较好做了：偏置网络、匹配网络、稳定性分析、仿真、版图、流片，基本上没有任何关隘了。另外，计划同一批流片的还有几个版本的分频器--原理图已经仿真OK；还有泰哥的VCO，他的试验板结果非常好。稍远一些的工作安排就是DAC、DDS，还有W波段PA的设计。
Go, go go!
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上周回家，按下。
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每天中午游泳1公里已经坚持了快两个月--书上说坚持三个月会有脱胎换骨的变化，但是--难道是突变？想起来猴子走钢丝的故事。小瑞也有了健身卡，也是每天都去，呵呵，兴致挺高啊。
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总感觉，有些人，很无理，无礼。随他去。
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III-Vs and Ge look to help CMOS
2008-06-13
From: compoundsemiconductor.net
Cracks are starting to appear in silicon CMOS. Although the International Technology Roadmap for Semiconductors states that MOSFETs with strained silicon channels will be suitable down to the 22 nm node and possibly beyond, projections of device performance indicate otherwise. Studies show a gap will appear between projected and actual performances as node sizes fall to less than 65 nm, and this will only get wider with increased scaling (figure 1).
To make matters worse, history suggests that one of the main sources for transistor improvement is an increase in channel carrier velocity. Recent work by MIT's Ali Khakifirooz reveals that this depends more strongly on low field mobility than was previously believed, which will make it even harder for silicon CMOS to stick to its roadmap.
Fortunately, it should be possible to improve channel mobility significantly by switching to other materials, such as III-Vs and germanium. III-Vs promise to increase electron mobility by 10–30 times, which makes them great candidates for high-speed, low-power n-channel transistors. However, they cannot make good p-channels, which are also needed for CMOS, because their hole mobilities are relatively low. This is where germanium comes in – it has a hole mobility four times that of silicon.
Turning to other materials is not a new idea. In 1986, prototype 16- and 32-bit GaAs RISC processors were developed by Vitesse Electronics Corporation and Texas Instruments. These delivered fast clock speeds of up to 200 MHz, but they were a commercial failure due to high costs and high power consumption. The history of germanium dates back even farther, but this element hasn't been used in mainstream FETs for decades. However, there is good reason to believe that the time has come for III-Vs and germanium to make a lasting impact.
For one thing, the industry is very short of options. It would prefer to steer clear of even more immature technologies, which rules out transistors employing graphene as the channel material and FETs operating via impact ionization or quantum mechanical tunneling. This means that germanium and III-V MOSFETs will be the only real alternatives to silicon in the coming years. Encouragingly, research by Jesús del Alamo's group at MIT, as well as a partnership between Intel and QinetiQ, has delivered some promising results with III-V n-channel HEMTs. These efforts have shown that III-V FETs can be less power hungry and faster than their silicon counterparts at the low supply voltages required for billion-transistor integration.
However, before we get carried away, it's important to realize that there are some massive hurdles to overcome before we can fabricate non-silicon channels in CMOS. These dwarf those that were faced by the industry when it made the recent transition from traditional SiO2 to high-k dielectrics.
Dictated by economics, FETs with non-silicon channels will have to be realized on large-area silicon substrates. This presents a tremendous challenge because it is difficult to unite materials into a near-perfect single-crystal epistructure when they have different thermal expansion coefficients, lattice constants and, in the case of III-Vs, crystal types. Many hours have been thrown at this problem and, although there has been an intensified effort in recent times, potential roadblocks still remain.
Non-silicon transistors are also susceptible to poor off-state performance resulting from the narrower bandgap of the material employed – InGaAs, InAs, InSb or germanium. This increases band-to-band tunneling at the high electric fields that exist at the drain side of the gate of scaled devices, which increases leakage current and cuts the transistor's Ion/Ioff ratio. The density of states available for conduction in high-mobility III-V channels is also less than one-hundredth of that for silicon equivalents.
Some of these changes in material characteristics hinder the performance of inversion-type MOSFETs, the standard workhorse of silicon CMOS. Minority carrier mobilities in surface inversion channels are relatively low. Large surface potentials are needed to produce the surface inversion required for transistor operation, leading to a narrowing of surface quantum wells with large energy quantization, which further reduces the density of states and leads to an increase in the proportion of electrons scattered into satellite valleys. In short, inversion-type MOSFETs may not be the best option for III-Vs.
However, recent work at various groups, including Freescale, the University of Glasgow, UK, and Interuniversity Microelectronics Center (IMEC), Belgium, has shown that it is possible to address some of the problems associated with non-silicon MOSFETs. For example, efforts at Freescale have revealed that progress can be made on the III-V side by turning to flatband- or accumulation-mode MOSFETs, which are promising high-mobility devices.
Flatband MOSFETs
Although the flatband MOSFET is similar to its inversion-mode equivalent – it shares planarity, enhancement-mode terminal characteristics and the ability to be implemented as either a surface or a buried channel device – there are fundamental differences in device operation. The flatband-mode MOSFET, unlike its inversion-mode cousin, is a majority carrier device in the on state and a minority carrier device in the off state. This means that the transistor is able to benefit from the higher majority carrier mobility and increased on-state current, in addition to the potentially lower off-state leakage current. This reduction in the leakage current can result from both deep depletion within the device and minority carrier extraction measures.All non-silicon MOSFET developers face the challenge of fabricating a satisfactory oxide interface. For decades the only material capable of producing a good enough interface for device operation was a combination of silicon and oxygen. Even today the leading CMOS manufacturers insert a thin SiO2 interfacial layer between silicon and a high-k dielectric. However, promising contenders are emerging for device quality interfaces on germanium, such as ultrathin fully strained epitaxial silicon layers and thermally grown GeO2 with in situ deposited high-k dielectrics. It is also possible to make device-quality oxide–semiconductor interfaces for GaAs-based MOSFETs by depositing Ga2O molecules into the arsenic dimers of a clean GaAs surface. Conventional oxidation – the process used for elemental semiconductors – is not an option because it produces a high density of trap levels within the GaAs bandgap.
Heterogeneous integration is clearly an important challenge but it is not the only criterion for judging the progress of non-silicon FETs. After all, it is not just the device's performance that matters but also its suitability for incorporation into CMOS.
The Intel and MIT groups have built some high-performance n-channel III-V PHEMTs that have a gate length of less than 100 nm, high-channel electron mobilities of 10,000–20,000 cm2/Vs and a superior gate delay and power-delay-product compared with state-of-the-art silicon NMOS transistors. However, their Schottky contact gate electrodes limit scalability and progress in this area will require the addition of oxide layers to address CMOS requirements.
One device that shows promise for fulfilling CMOS requirements is the GaAs-based n-channel MOSFET that we have developed at Freescale and the University of Glasgow. This flatband-mode device, which features a Ga2O/GaAs interface and an In0.3Ga0.7As channel, has been developed for radio-frequency applications and delivers a superior performance to PHEMTs (figure 3). More important is that it has the potential to usurp BiHEMT and BiFET technologies and kick-start a new era of RF front-end integration in applications such as mobile handsets. Success in this market would be driven by the planar MOS configuration, which employs a common epitaxial layer structure allowing single-chip integration of power amplification, RF switching, and digital and analog functions.
These MOSFETs are of limited relevance for CMOS due to their lower mobility compared with higher indium mole fraction InGaAs channel layers. Introducing indium into this layer with a mole fraction of 50% or more requires a switch from a GaAs to an InP substrate. At Freescale we have done this and built a thin-body structure that contains an In0.75Ga0.25As channel by MBE (figure 4). This epiwafer has a mobility of 8000 cm2/Vs, but other MOSFET wafers with similar layer structures have shown electron mobilities of more than 10,000 cm2/Vs – 20 times as great as silicon NMOS.
Our flatband-mode InP MOSFETs deliver an impressive on-state performance – transconductance exceeds 700 µS/µm for a 1 µm gate length. This compares favorably with InGaAs MOSFETs built by both Peide Ye's group from Purdue University and a collaboration between IBM and Princeton. They feature gate oxides deposited by atomic layer deposition, and they have electron mobilities and a transconductance of 1200 cm2/Vs and 230 µS/µm, respectively.
Germanium inversion-mode MOSFETs with a thin epitaxial silicon layer are being developed by IMEC. Such devices can deliver peak hole channel mobilities of more than 350 cm2/Vs on unstrained p-channel devices. Mobility increases to more than 640 cm2/Vs on strained devices – three times as high as the peak value for silicon.
Optimizing implantations and silicon passivation leads to good control of short channel effects and enables devices with a peak transconductance of 800 µS/µm for a 125 nm channel length. At 1.5 V drain voltage this transistor delivers 722 µA/µm – more than double that of a p-channel silicon MOSFET with a 120 nm channel.
If III-V and germanium channel MOSFETs are to provide a viable future beyond silicon CMOS then they will have to scale to diminutive CMOS dimensions. However, it's not just a question of physical miniaturization as these transistors must deliver enhanced electron or hole transport properties. In addition, and in contrast to GaAs MOSFETs, there is still the problem of making a high-quality oxide–semiconductor interface for III-V channel materials with CMOS relevance. This problem plagues all of today's high indium mole fraction channel technologies, and it is evident from the difficulty associated with turning the device off (figure 5).
"Everything can be done in silicon" is a claim that our community contests. And with the scaling of CMOS feature sizes delivering diminishing returns, there is reason to believe that with a collaborative spirit the compounds and germanium can gain a solid foothold. Indeed, it is possible that the saying "everything can be done on silicon" will eventually find universal acceptance. But whatever the outcome for non-silicon MOSFETs for CMOS, one thing is certain: the semiconductor community has some exciting and challenging years ahead.
Further reading
A Khakifirooz et al. IEEE Transactions on Electron Devices 55 (in press).
J R Lineback 1986 Electronics June 9 21.
B C Cole 1986 Electronics September 18 57.
S Datta et al. 2005 IEDM Technical Digest 763.
D H Kim et al. 2007 IEDM Technical Digest 629.
R Metzger 2007 May Compound Semiconductor 16.
M Passlack 2006 IEEE Transactions on Electron Devices 53 2773.
A Delabie et al. 2007 Appl. Phys. Lett. 91 082904.
M Hale et al. 2003 J. Chemical Physics 119 6719.
R J W Hill et al. 2007 IEEE Electron Device Letters 28 1080.
R J W Hill et al. 2008 Electronics Letters 44 498.
Y Yuan et al. 2007 IEDM Technical Digest 637.
G Nicholas et al. 2007 IEEE Electron Device Letters 28 825.
M K Hudait et al. 2007 IEDM Technical Digest 625.
About the authorJoining Motorola in 1995 from AT&T Bell Laboratories, Matthias Passlack led and contributed to R&D efforts at Motorola and Freescale Semiconductor in the field of III-V MOS materials, processes, characterization, devices and physics. He left Freescale in March. Marc Heyns joined IMEC in 1986. He became an IMEC fellow in 2001 and a professor at the KU Leuven in 2005. His current research topics include novel high-k dielectric materials, advanced cleaning and surface preparation, and novel devices made on high-mobility substrates, such as germanium and III/V, nanowires, carbon nanotubes and graphene. Iain Thayne has worked on III-V materials and transistors for 23 years, initially at Philips Research Labs and since 1998 at the University of Glasgow, where he is professor of ultrafast systems. He coordinates III-V MOSFET research funded by the UK EPSRC, the US SRC and the EU.
Richard: 总有令人激动的技术。
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两篇报道
2008-06-13
近日，微电子所在新型微波功率放大器模块研究领域获得突破性进展。中国科学院微电子研究所—四川龙瑞微电子联合实验联合研制成功的Ku波段功率放大器模块，在13.7-14.5GHz频率范围内，功率增益 ，输出峰值功率 ，总工作效率达到13.6%。该模块有效体积为 ，总体重量为 ，并且通过了严格的高低温可靠性测试，关键技术指标都达到了国内一流水平。
该模块采用结构简单并且可靠性高的平面微带线完成微波链路，有效减小了重量和体积。在机械结构上设计了新颖的双层腔体，将微波电路和控制电路、偏置电路等进行隔离，消除了高频和低频电路的相互影响，并且提高了模块的可靠性。针对内匹配微波功率器件，设计了可以提高稳定性、宽带性能、低频振荡抑制能力及谐波抑制能力的偏置电路。采用先进的设计方法及工艺技术，成功攻克了微波功率放大器设计中的寄生振荡、参量振荡和效率衰退等难题，在有效载荷、效率等方面创造了国内记录，拥有完全自主知识产权。
Ku波段微波功率放大器模块是卫星通信等应用领域的核心部件。随着应用系统的不断演进，研制小型化、大功率、高效率和高可靠性的微波功率放大器模块，具有重要意义。
继前不久成功研制出Ku波段功率放大器模块后，微电子所在此基础上又研制成功了Ka波段大功率模块，在新型微波功率放大器模块研究领域再次获得重大进展。
此次研制成功的Ka波段功率放大器模块，在30-38GHz工作频率范围内，输出峰值功率Ppk≥15W，功率增益Gp≥55dB，总工作效率在全频段内≥13%。模块的有效体积为 ，总体重量 。所有关键技术指标都达到了国内一流水平，部分技术达到国际先进水平。
该模块采用全波导结构，具有低损耗、高效率、驻波良好的特点。独特的波导合成结构，实现了毫米波功率放大器的模块化设计，易于级联实现更大输出功率，初步级联试验已经突破百瓦量级，拥有完全的自主知识产权。
随着毫米波技术的广泛应用，对毫米波信号源的输出功率也提出了越来越高的要求。目前，单个固态器件的输出功率因受到散热、阻抗匹配、工艺的限制而无法达到应用的要求，必须开展功率放大模块的研制。新颖的波导合成结构的提出，既可以保证高的合成效率，也将微波链路损耗降到最低。同时，创造性的可定制、可级联模块化设计，便于实现更大规模功率的输出，具有极强的市场竞争力。该模块的研制成功为研究所在毫米波大功率器件及模块研究领域提供了重要的自主创新平台。
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高频S参数测试中的去嵌入
2008-06-05
好长时间没有更新Blog了，看paper看得满脑子都是VBIC了，今天灌一篇，说一下测试和建模。
S参数测试中的去嵌入问题，以前觉得挺高深的，但是实际做过之后也不觉得有多困难了--当然，如果精度要求很高的话就另当别论了。在画版图的时候，除了器件之外一般还要有用于去嵌入的Open和Short图形，Open图形用来去除寄生电容的影响，Short图形用来去除寄生电感和电阻的影响。去嵌入的一般步骤如下：
（1）测量Open图形的Y参数[Yo]与Short图形的Y参数[Ys]；
（2）用[Ys]减去[Yo]，得到：[Yso]=[Ys]-[Yo]；
（3）将[Yso]换为Z参数[Zso]，得到互连线寄生电感和电阻；
（4）将器件S参数换为Y参数[Yd]；
（5）用[Yd]减去[Yo]，得到：[Ydo]=[Yd]-[Yo]，去除了寄生电容；
（6）将[Ydo]换为Z参数[Zdo]；
（7）用[Zdo]减去[Zso]，得到：[Zdem]=[Zdo]-[Zso]，去除了寄生电感和电阻；
（8）最后将[Zdem]换为S参数[Sdem]，即为器件去嵌入之后的本征S参数。
测试在ICCAP和Probe Station平台上完成--注意测试参考平面的校准；处理可以在ADS中方便地完成。
另外，这段时间在葛霁师兄的指导下做了我们的Q10_RE10 HBT的建模工作。最大感触是：很多工作，只有动手去做，才能真正理解，靠paper是永远不能解决问题的。经过一系列繁琐的测试、去嵌入及数据处理工作之后，终于得到一套比较完整的VBIC模型参数。下图是我的S参数拟合曲线：
似乎误差还在可以接受的范围之内，反正也存在工艺稳定性的误差，所以也不必苟求严丝合缝。测试其实很快，关键是数据处理比较复杂：Flyback，Foward G-P，Reverse G-P，Cold-Capacitance，Forced-Vbe I-V，Forced-Ibe I-V，Active S-parameters等等，还要拟合和优化。不得不说的一点是：VBIC模型的初始参数对于拟合的收敛至关重要。
还有就是上周的Load-pull测试了。新的Load-pull非常棒，校准之后测试非常简单。我一个人花了半个下午加半个晚上的时间就完成了一个Wafer上器件的三频点抽测，得到一堆数据。从测试结果上看，我们的工艺一致性和稳定性还是不错的，但是在测试当中发现一个问题：
1. 4GHz： Zopt=44.6502+34.4645j;
2. 6GHz: Zopt=10.6537-14.1309j;
3. 8GHz: Zopt=101.3300+46.057j。在频率6GHz的时候，Zopt表现为容性--而且同一Wafer上不同区域的很多器件都是这样，那么就是说我们的器件在6GHz表现出感性。以前从来没有见过这种性质，而且按照Cripps先生的理论分析，似乎也不会出现这种情况。考虑了很久，似乎有一个比较合理的解释：寄生，自谐振，但是无法证明。
***
顺便说一下上周末参加的USTC北京校友大会。科大50年前在玉泉路成立，到现在，走过了一段不平凡的历史。那天我去做了志愿者，和很多传说中的人物亲密接触，见到了很多偶像--比如张亚勤，赵忠贤，黄吉虎等等。提起黄吉虎老师--传说中的一大名捕，他老人家真是风趣幽默，给我们讲述了当年钱学森先生给他们考试的事情--这个早有传说，但没想到是真事情：两道题，考了一整天，晕倒四名学生，并且开根号乘以十也来源于此事。科大人身上，有一种特质，我只能感受，但说不出来，也许可以叫做：不凡。
***
上周的上海之行，和两个土人再聚首，唯有感叹时光如梭！
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A new market for GaAs PAs
2008-05-28
From: compoundsemiconductor.net
The emerging market for so-called femtocells will explode over the next five years, providing a key new application for power amplifier (PA) components, and a likely boost for makers of GaAs devices.
Reports from ABI Research, In-Stat and Wintergreen Research all predict a sharp increase in deployments of femtocells, with accompanying demand for the various semiconductor components that they require.
Femtocells, which are miniature cellular base stations, are increasingly viewed as the best solution to providing reliable broadband cellular connectivity inside homes and offices.
As anybody living in a house with thick stone walls will attest, indoor cellular reception can be extremely variable. That’s because the high-frequency signals being transmitted between a cellular handset and a remote base station are absorbed to varying degrees depending on the specific location of the two.
For conventional mobile services like voice calls and simple messaging, that isn't much of a problem – but with demand for data-hungry services increasing, broadband coverage needs to be less patchy and more reliable.
Now it seems that some network operators have concluded that the most cost-effective way of ensuring that kind of coverage is for customers who want broadband cellular access to deploy femtocells in their homes and workplaces.
The US market analysis company Wintergreen Research recently issued a report forecasting that global shipments of the tiny base stations, which today stand at virtually zero, will grow to nearly 48 million in 2012 as the predicted cost of the cells drops to just $100.
In a less bullish report, In-Stat predicts 31 million unit shipments of femtocells and related picocell and microcells by the same year.
"One barrier to roll-out is the need to reduce the cost per unit of the hardware," states the Wintergreen report. "Initially it may be that operators provide femtocells to customers as part of a service plan."
Wintergreen analysts Susan Eustis and Ellen Curtiss note that major companies such as fiber-optic networking giant Cisco Systems have a vested interest in femtocells, because the technology could ultimately be integrated into consumer hardware like set-top boxes, which Cisco already sells.
"Calls would go from the handset, to the femtocell, down the broadband connection, and back onto the cellular network," they explain. "This beats having to set up lots more [conventional] base stations."
In another report, Stuart Carlaw from ABI Research predicts that the market for semiconductors used in femtocell applications will grow from less than $72 million in 2008 to nearly $2 billion by 2013.
As always, that market will be dominated by silicon devices, but femtocells will also require power amplifiers operating at cellular frequencies – an application dominated by GaAs at the handset level, but by silicon LDMOS in conventional base stations.
Because femtocell signals are designed to operate over only a short range, the high power of silicon LDMOS technologies is not a pre-requisite, suggesting that incumbent handset PA suppliers like RF Micro Devices and Skyworks Solutions may be at an advantage.
Skyworks Solutions has already made inroads into the early market, and is supplying Samsung with four types of components for use in the Korean firm's femtocells, including the wideband-CDMA SKY77410 power amplifier.
Although the unit demand from femtocells might not match that from mobile handsets initially, the Wintergreen analysts believe that when the cost of the technology drops to $100, things will really take off, with an anticipated 95.5 million unit shipments in 2014.
The numbers quoted by the various analyst reports differ widely, but they do all agree that femtocells are emerging as a key cellular technology:
"3G services will have limited success without addressing the indoor coverage issue," says In-Stat's report. "The cost to address these shortcomings with traditional macro base station solutions is too high, and not possible for most mobile operators."
In-Stat analyst Allen Nogee added: "Microcells, picocells, and femtocells address these challenges in a much more cost-effective manner."
"By providing smaller and less powerful base stations in smaller areas, like public spaces, offices, and even homes, carriers can provide better coverage in more specific areas without a huge capital investment."
***
这次来上海，似乎对上海的印象好了一些。
Complex Precision.
业精于勤
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